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RMPA1959
September 2004
RMPA1959
PCS 3.4V CDMA & CDMA2000-1X PowerEdgeTM Power Amplifier Module
General Description
The RMPA1959 power amplifier module (PAM) is designed for CDMA and CDMA2000-1X personal communications system (PCS) applications. The 2 stage PAM is internally matched to 50 to minimize the use of external components and features advanced DC power management to reduce current consumption during peak phone usage. High power-added efficiency and excellent linearity are achieved using our InGaP Heterojunction Bipolar Transistor (HBT) technology.
Features
* Single positive-supply operation and low power and shutdown modes * 39% CDMA efficiency at +28dBm average output power * Compact LCC package- 4.0 x 4.0 x 1.5 mm with industry standard pinout * Internally matched to 50 and DC blocked RF input/ output. * Meets CDMA2000-1XRTT performance requirements
Device
Absolute Ratings1
Symbol Vcc1, Vcc2 Vref Vmode Pin TSTG Parameter Supply Voltages Reference Voltage Power Control Voltage RF Input Power Storage Temperature Min 0 2.6 0 - -55 Max 5.0 3.5 3.5 +10 +150 Units V V V dBm C
Note: 1: No permanent damage with only one parameter set at extreme limit. Other parameters set to typical values.
(c)2004 Fairchild Semiconductor Corporation
RMPA1959 Rev. D
RMPA1959
Module Block Diagram
VCC1, VCC2 (1, 10)
COLLECTOR BIAS
PA MODULE
GND (3, 6, 7, 9, 11)
INTERSTAGE MATCH
RF IN (2)
INPUT MATCHING NETWORK
INPUT STAGE
MMIC
OUTPUT STAGE
OUTPUT MATCHING NETWORK
RF OUT (8)
INPUT STAGE BIAS
OUTPUT STAGE BIAS
VCC=3.4V (nom) VREF=2.85V (nom) 1850-1910 MHz 50 Ohms I/O
VREF (5)
BIAS CONTROL
Vmode (4)
Figure 1. RMPA1959 US PCS CDMA Power Amplifier Module Functional Block Diagram
Electrical Characteristics1
Symbol Parameter Operating Frequency f CDMA Operation Small-Signal Gain SSg Gp PO PAEd Power Gain Linear Output Power PAEd (digital) @ +28 dBm PAEd (digital) @ +16 dBm PAEd (digital) @ +16 dBm High Power Total Current Low Power Total Current Adjacent Channel Power Ratio 1.25 MHz Offset 2.25 MHz Offset Condition Min 1850 23 25 28 16 36 39 10 20 460 120 -50 -52 -60 -68 2.5:1 PO +28dBm; 1850 to 1910 MHz PO +28dBm Load VSWR 5.0:1 No permanent damage -30 Vmode 2.0V PO +28dBm No applied RF signal 50 5 1 2.0:1 4 -139 -30 -60 10:1 85 Typ Max 1910 Units MHz dB dB dB dBm dBm % % % mA mA dBc dBc dBc dBc
PO = 0dBm PO = +28dBm, Vmode = 0V PO = +16dBm, Vmode 2.0V Vmode = 0V Vmode 2.0V Vmode = 0V Vmode 2.0V Vmode 2.0V, VCC = 1.4V PO = +28dBm, Vmode = 0V PO = +16dBm, Vmode = 2.0V IS-95 PO = +28dBm; Vmode = 0V PO = +16dBm; Vmode = 2.0V PO = +28dBm; Vmode = 0V PO = +16dBm; Vmode = 2.0V
25 28 24.5
Itot
530
ACPR1 ACPR2
-46 -57
General Characteristics VSWR Input Impedance Noise Figure NF Rx No Receive Band Noise Power 2fo-5fo Harmonic Suppression Spurious Outputs2,3 S Ruggedness w/Load Mismatch3 Case Operating Temperature Tc DC Characteristics Quiescent Current Iccq Reference Current Iref Icc (off) Leakage Shutdown Current
dB dBm/Hz dBc dBc C mA mA A
8 5
Notes: 1: All parameters met at Tc = +25C, Vcc = +3.4V, f = 1880 MHz, and load VSWR 1.2:1. 2: All phase angles. 3: Guaranteed by design
(c)2004 Fairchild Semiconductor Corporation RMPA1959 Rev. D
RMPA1959
I/O 1 INDICATOR TOP VIEW 1 2 (4.00mm -.050 ) SQUARE
+.100
10 9
3 4 5
PA1959 PPYYWW U31XX
8 7 6
1.60mm MAX. FRONT VIEW .25mm TYP. 3.50mm TYP. SEE DETAIL A .40mm .10mm .30mm TYP. .85mm TYP. 11 2 1 1.08mm 1.84mm BOTTOM VIEW .18mm DETAIL A TYP. 3.65mm .10mm .40mm .45mm
Figure 2. Package Outline
Package Pinout
Parameter RF DC Power Ground Control Symbol RF In RF Out Vcc1 Vcc2 Gnd Vmode Vref Description RF Input Signal RF Output Signal Supply Voltage to Input Stage Supply Voltage to Output Stage Signal Ground Paddle Ground High Power/Low Power Mode Control Reference Voltage Pin# 2 8 1 10 3, 6, 7, 9 11 4 5
(c)2004 Fairchild Semiconductor Corporation
RMPA1959 Rev. D
RMPA1959
MATERIALS LIST QTY ITEM NO. 1 2 5 REF 3 3 2 1 1 A/R A/R 1 2 3 4 5 PART NUMBER G657553-1 V2 #142-0701-841 #2340-5211TN G657584 GRM39X7R102K50V DESCRIPTION PC, BOARD SMA CONNECTOR TERMINALS ASSEMBLY, RMPA1959 1000 pF CAPACITOR (0603) 1000 pF CAPACITOR (0603) 3.3 F CAPACITOR (1206) 0.1F CAPACITOR (0603) 0.1F CAPACITOR (0603) SOLDER PASTE SOLDER PASTE VENDOR FAIRCHILD JOHNSON 3M FAIRCHILD MURATA PANASONIC TDK MURATA PANASONIC INDIUM CORP. INDIUM CORP.
5 (ALT) ECJ-1VB1H102K 6 7 C3216X5R1A335M GRM39Y5V104Z16V
7 (ALT) ECJ-1VB1C104K 8 9 SN63 SN96
Figure 3. Evaluation Board Layout
DC Turn-On Sequence
1) Vcc1 = Vcc2 = 3.4V (typ) 2) Vref = 2.85V (typ) 3) High-Power: Vmode = 0V (Pout > 16dBm) Low-Power: Vmode = 2.0V (Pout < 16dBm)
(c)2004 Fairchild Semiconductor Corporation
RMPA1959 Rev. D
RMPA1959
Evaluation Board Schematic
3.3 F Vcc1 SMA1 RF IN 1000 pF 1 2 50 ohm TRL Vmode Vref 1000 pF 0.1 F 1000 pF 10 50 ohm TRL 3.3 F Vcc2
4 5
PA1959 PPYYWW U31XX
11 (package base)
8
SMA2 RF OUT
3,6,7,9
Recommended Operating Conditions
Parameter Operating Frequency Supply Voltage Reference Voltage (operating) (shutdown) Bias Control Voltage (low-power) (high-power) Linear Output Power (high-power) (low-power) Case Operating Temperature Symbol f Vcc1, Vcc2 Vref Vmode Pout Tc -30 Min 1850 3.0 2.7 0 1.8 0 Typ 3.4 2.85 2.0 Max 1910 4.2 3.1 0.5 3.0 0.5 +28 +16 +85 Units MHz V V V V V dBm dBm C
(c)2004 Fairchild Semiconductor Corporation
RMPA1959 Rev. D
RMPA1959
Performance Data
RMPA1959 Vcc=3.4V, Vref = 2.85V, Pout=28dBm, Vmode=0V 33 32 31 Gain (dB) PAE (%) 30 29 28 27 26 25 1840 1860 1880 Frequency (MHz) 1900 1920 43 42 41 40 39 38 37 36 35 1840 RMPA1959 Vcc=3.4V, Vref = 2.85V, Pout=28dBm, Vmode=0V
1860
1880 Frequency (MHz)
1900
1920
RMPA1959 Vcc=3.4V, Vref = 2.85V, Pout=28dBm, Vmode=0V, IS-95 -45 -46 -47 -48 APCR1 (dBc) -49 -50 -51 -52 -53 -54 -55 1840 1860 1880 Frequency (MHz) RMPA1959 16dBm Pout Vcc = 3.4V, Vref = 2.85V Vmode = 2.0V 28 27 26 Gain (dB) 25 24 23 22 1840 8 PAE (%) 10 12 1900 1920 ACPR2 (dBc) -55 -56 -57 -58 -59 -60 -61 -62 -63 -64
RMPA1959 Vcc=3.4V, Vref = 2.85V, Pout=28dBm, Vmode=0V, IS-95
-65 1840
1860
1880 Frequency (MHz) RMPA1959 16dBm Pout Vcc = 3.4V, Vref = 2.85V Vmode = 2.0V
1900
1920
11
9
1860
1880 Frequency (MHz) RMPA1959 16dBm Pout Vcc = 3.4V, Vref = 2.85V Vmode = 2.0V
1900
1920
7 1840
1860
1880 Frequency (MHz) RMPA1959 16dBm Pout Vcc = 3.4V, Vref = 2.85V Vmode = 2.0V
1900
1920
-40
-60
-45 APCR1 (dBc) APCR2 (dBc) 1860 1880 Frequency (MHz) 1900 1920
-65
-50
-70
-55
-75
-60 1840
-80 1840
1860
1880 Frequency (MHz)
1900
1920
(c)2004 Fairchild Semiconductor Corporation
RMPA1959 Rev. D
RMPA1959
Efficiency Improvement Application
In addition to high-power/low-power bias modes, the efficiency of the PA module can be significantly increased at backed-off RF power levels by dynamically varying the supply voltage (Vcc) applied to the amplifier. Since mobile handsets and power amplifiers frequently operate at 10-20 dB back-off, or more, from maximum rated linear power, battery life is highly dependent on the DC power consumed at antenna power levels in the range of 0 to +16 dBm. The reduced demand on transmitted RF power allows the PA supply voltage to be reduced for improved efficiency, while still meeting linearity requirements for CDMA modulation with excellent margin. High-efficiency DC-DC converters are now available to implement switched-voltage operation. The following figures show measured performance of the PA module in low-power mode (Vmode = +2.0V) at +16dBm output power and over a range of supply voltages from 3.4V nominal down to 1.2V. Power-added efficiency is more than doubled from 10 percent to nearly 25 percent (Vcc = 1.2V) while maintaining a typical ACPR1 of -52dBc and ACPR2 of less than -61dBc. Operation at even lower levels of Vcc supply voltage are possible with a further restriction on the maximum RF output power. As shown below, the PA module can be biased at a supply voltage of as low as 0.7V with an efficiency as high as 10-12 percent at +8dBm output power. Excellent signal linearity is still maintained even under this low supply voltage condition.
RMPA1959 PCS 4x4mm2 PAM Vref = 2.85V, Pout=16dBm 30 29 28 27 Gain (dB) 26 25 24 23 22 21 20 1840 1860 1880 Frequency (MHz) 1900 1920 5 1840 Vcc=2.0V Vcc=1.5V Vcc=1.2V 10 Vcc=3.4V Vcc=3.0V PAE (%) 30 25 20 35
RMPA1959 PCS 4x4mm2 PAM Vref = 2.85V, Pout=16dBm
Vcc=1.2V Vcc=1.5V Vcc=2.0V
15 Vcc=3.0V Vcc=3.4V 1860 1880 Frequency (MHz) 1900 1920
RMPA1959 PCS 4x4mm2 PAM Vref = 2.85V, Pout=16dBm -40 -42 -44 -46 ACPR1 (dBc) -48 -50 -52 -54 -56 -58 -60 1840 1860 1880 Frequency (MHz) 1900 1920 Vcc=1.2V Vcc=1.5V Vcc=2.0V Vcc=3.0V Vcc=3.4V -55 -57 -59 ACPR2 (dBc) -61 -63 -65 -67 -69 -71 -73 -75 1840
RMPA1959 PCS 4x4mm2 PAM Vref = 2.85V, Pout=16dBm
Vcc=1.2V Vcc=2.0V
Vcc=1.5V
Vcc=3.4V
Vcc=3.0V
1860
1880 Frequency (MHz)
1900
1920
(c)2004 Fairchild Semiconductor Corporation
RMPA1959 Rev. D
RMPA1959
Efficiency Improvement Application (continued)
RMPA1959 PCS 4x4mm2 PAM Vref = 2.85V, Pout=16dBm, Freq=1.88GHz 30 28 25 26 Gain (dB) 24 22 20 10 18 16 0.5 1 1.5 2 2.5 Vcc (V) 3 3.5 4 5 0.5 1 1.5 2 2.5 Vcc (V) 3 3.5 4 PAE (%) 20 30 RMPA1959 PCS 4x4mm2 PAM Vref = 2.85V, Pout=16dBm, Freq=1.88GHz
15
RMPA1959 PCS 4x4mm2 PAM Vref = 2.85V, Pout=16dBm, Freq=1.88GHz -40 -42 -44 ACPR1 (dBc) -48 -50 -52 -54 -56 -58 -60 0.5 1 1.5 2 2.5 Vcc (V) 3 3.5 4 ACPR2 (dBc) -46 -55 -57 -59 -61 -63 -65 -67 -69 -71 -73 -75 0.5
RMPA1959 PCS 4x4mm2 PAM Vref = 2.85V, Pout=16dBm, Freq=1.88GHz
1
1.5
2
2.5 Vcc (V)
3
3.5
4
RMPA1959 PCS 4x4mm2 PAM Vref = 2.85V, Pout=8dBm, Freq=1.88GHz 30 28 26 Gain (dB) 24 22 20 18 16 0.5 1 1.5 2 2.5 Vcc (V) 3 3.5 4 PAE (%) 16 14 12 10 8 6 4 2 0 0.5 1
RMPA1959 PCS 4x4mm2 PAM Vref = 2.85V, Pout=8dBm, Freq=1.88GHz
1.5
2
2.5 Vcc (V)
3
3.5
4
RMPA1959 PCS 4x4mm2 PAM Vref = 2.85V, Pout=8dBm, Freq=1.88GHz -45 -47 -49 ACPR1 (dBc) -53 -55 -57 -59 -61 -63 -65 0.5 1 1.5 2 2.5 Vcc (V) 3 3.5 4 ACPR2 (dBc) -51 -60 -62 -64 -66 -68 -70 -72 -74 -76 -78 -80 0.5 1
RMPA1959 PCS 4x4mm2 PAM Vref = 2.85V, Pout=8dBm, Freq=1.88GHz
1.5
2
2.5 Vcc (V)
3
3.5
4
(c)2004 Fairchild Semiconductor Corporation
RMPA1959 Rev. D
RMPA1959
Application Information
CAUTION: THIS IS AN ESD SENSITIVE DEVICE
Precautions to Avoid Permanent Device Damage: * Cleanliness: Observe proper handling procedures to ensure clean devices and PCBs. Devices should remain in their original packaging until component placement to ensure no contamination or damage to RF, DC & ground contact areas. * Device Cleaning: Standard board cleaning techniques should not present device problems provided that the boards are properly dried to remove solvents or water residues. * Static Sensitivity: Follow ESD precautions to protect against ESD damage: - A properly grounded static-dissipative surface on which to place devices. - Static-dissipative floor or mat. - A properly grounded conductive wrist strap for each person to wear while handling devices. * General Handling: Handle the package on the top with a vacuum collet or along the edges with a sharp pair of bent tweezers. Avoiding damaging the RF, DC, & ground contacts on the package bottom. Do not apply excessive pressure to the top of the lid. * Device Storage: Devices are supplied in heat-sealed, moisture-barrier bags. In this condition, devices are protected and require no special storage conditions. Once the sealed bag has been opened, devices should be stored in a dry nitrogen environment. Device Usage: Fairchild recommends the following procedures prior to assembly. * Dry-bake devices at 125C for 24 hours minimum. Note: The shipping reels cannot withstand 125C baking temperature. * Assemble the dry-baked devices within 7 days of removal from the oven. * During the 7-day period, the devices must be stored in an environment of less than 60% relative humidity and a maximum temperature of 30C * If the 7-day period or the environmental conditions have been exceeded, then the dry-bake procedure must be repeated. Solder Materials & Temperature Profile: Reflow soldering is the preferred method of SMT attachment. Hand soldering is not recommended. * Reflow Profile - Ramp-up: During this stage the solvents are evaporated from the solder paste. Care should be taken to prevent rapid oxidation (or paste slump) and solder bursts caused by violent solvent out-gassing. A typical heating rate is 1- 2C/sec. - Pre-heat/soak: The soak temperature stage serves two purposes; the flux is activated and the board and devices achieve a uniform temperature. The recommended soak condition is: 120-150 seconds at 150C. - Reflow Zone: If the temperature is too high, then devices may be damaged by mechanical stress due to thermal mismatch or there may be problems due to excessive solder oxidation. Excessive time at temperature can enhance the formation of intermetallic compounds at the lead/board interface and may lead to early mechanical failure of the joint. Reflow must occur prior to the flux being completely driven off. The duration of peak reflow temperature should not exceed 10 seconds. Maximum soldering temperatures should be in the range 215-220C, with a maximum limit of 225C. - Cooling Zone: Steep thermal gradients may give rise to excessive thermal shock. However, rapid cooling promotes a finer grain structure and a more crackresistant solder joint. The illustration below indicates the recommended soldering profile. Solder Joint Characteristics: Proper operation of this device depends on a reliable voidfree attachment of the heatsink to the PWB. The solder joint should be 95% void-free and be a consistent thickness. Rework Considerations: Rework of a device attached to a board is limited to reflow of the solder with a heat gun. The device should not be subjected to more than 225C and reflow solder in the molten state for more than 5 seconds. No more than 2 rework operations should be performed.
(c)2004 Fairchild Semiconductor Corporation
RMPA1959 Rev. D
RMPA1959
240 220 200 183C 180 160 140 DEG (C) 120 100 80 60 40 20 0 0 60 120 TIME (SEC) 180 1C/SEC SOAK AT 150C FOR 60 SEC
10 SEC
45 SEC (MAX) ABOVE 183C
1C/SEC
240
300
Figure 4. Recommended Solder Reflow Profile
(c)2004 Fairchild Semiconductor Corporation
RMPA1959 Rev. D
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks.
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DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component is any component of a life 1. Life support devices or systems are devices or support device or system whose failure to perform can systems which, (a) are intended for surgical implant into be reasonably expected to cause the failure of the life the body, or (b) support or sustain life, or (c) whose support device or system, or to affect its safety or failure to perform when properly used in accordance with instructions for use provided in the labeling, can be effectiveness. reasonably expected to result in significant injury to the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Product Status Formative or In Design Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design.
Preliminary
First Production
No Identification Needed
Full Production
Obsolete
Not In Production
This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only.
Rev. I13

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